Missing a proper development system for your Atari 7800 ? Then RAMCart is probably what you are waiting for.

The RAMCart is basically an A7800 cartridge consisting of 512KByte of emulation SRAM, a 512KByte FLASH memory for the monitor software and a USB interface for downloading the code to the cartridge. An advanced programmable logic device is used to create the memory banking schemes and mapping.

The cartridge supports all the existing banking types and also adds a new bank type that adds extra flexibility for programmers. Although it is able to emulate all existing it is not really suitable for gaming when the programs always reside in RAM.

On the PC side there will be a debugger software capable of downloading the code to the system, setting breakpoints in the source code, single stepping code and performing all sorts of tasks that can ease the development phase.

Before I started the devlopment I created a brief document with what I considered to be the required functionality of the RAMCart system. You can download this document in the "Documentation" section on this page.


2006-04-30 Well, the progress is slow but steady. The debugger (NoIce) now connects securely to the RamCart and it is possible to download code to the SRAM. You can start and stop the downloaded code as well as insert breakpoints. I have tested the system quite extensively and it seem to be rather stable. There are some known traps you can fall into but with them known you should be able to work efficiently anyhow. So it now really is a true debugging tool. The PCB needs to be remade and the work to create a genuine debugger can start. So still some work to do.
2006-03-09 Time for another update.
I have been having problems to work up the energy to continue this project, but now I am happy report some progress.

The USB controller part has now been soldered on to the board with its companing components. When inserting the USB cable into the board, Windows detects the controller and installs the correct VCP drivers. I made a small test program that simply receives data from the PC via the USB controller with amazing speed. 32 Kbyte is just noticable. 

I can now continue the experiments with the NoIce debugger which will work as a test vehicle for the platform.

Anyway, in the process of getting this far I have discovered a number of minor flaws in the PCB layout which now makes the board look like an ants nest. But... most importantly it now works.

2006-02-05 Finally got the time to solder a RAM onto the board yesterday and after correcting some small quirks in the VHDL description the major parts now seem to be operating as they should. The FLASH can be read, written and erased. The RAM can be read and written and the background write mode (read the specfication for more detailed info) works as expected. I have removed the VHDL file from here as it continously changes and is probably always incorrect :-) Next part to build is the USB interface, will see if I have the time to do this sometime this week. 

I have now decided that the ROM monitor will permanently occupy the top 64 bytes of the memory map. I have estimated that this is sufficient to hold the reset and interupt service routines needed to service the ROM monitor and the user application. Unfortunatly as the 6502 does not have a separate BRK instruction interrupt vector there will be some overhead in the IRQ ISR for detecting the BRK instruction. If this becomes a problem one could always implement a way of mapping two different interupt vectors in the CPLD, thus creating a way of having one vector with BRK instruction detection support and one without.

Just to clearify one point, the NMI vector will reside in RAM directly ($FFFA, $FFFB) so there is no delay when servicing this interrupt.

Anyway, once a BRK instruction has been detected (because of a user breakpoint insertion) the rom monitor is mapped in and takes over the 7800, enabling all debugging features.

2006-01-25 Haven't had as much time as I would have wanted to to mess around with this project. I found one or two bugs in the VHDL code and have identified some issues that need to be addressed. I should be able to solder an SRAM this weekend and start testing the ROM monitor and debugger. I did an update to the design specification if anyone is interested in reading.
2006-01-22 Well after many long hours I decided to start building the second board and voila ! It works as a charm. Either the PCB was faulty on the first or I managed to destroy the CPLD device while soldering it to the board :-(
Anyway the project is now showing some progress again, I have now managed to read and write data to the FLASH memory on board. The next step is to solder an SRAM to the board and start testing the banking schemes in the CPLD. After that the USB device will be tested. Anyway if something happens, you can read about it here.
2006-01-21 Aaaaarghhh, something is terribly wrong. The first prototype I built just keeps locking my 7800 when it is inserted. Most signals keep on going like PHI2, R/W and others. But something is causing the CPU to fetch incorrect data. Something is altering either the address signals or the data signals. Ohh well, back to the lab now to hunt the problem out.
2006-01-17 This is the first entry and the current status is that the PCB's have been delivered and I just received the Xilinx CPLD's that should go onto the boards. So there will be some soldering done this weekend.


These documents are just here for reference and does probably not describe the current status of the project. I'll try to keep them updated but if you really want the latest you should probably contact me.

Design Specification ../docs/DesignSpecification_iet7820_pa2.pdf
Schematic ../docs/Schematic_pa1.pdf
VHDL description (removed for now)

If you have any question you can always contact me.

(C) Pontus Oldberg 2006
You can freely use any images, source code, text or other material from this site as long as it is for a non- commercial purpose. If you want to use something for any other purpose please contact me.